roko1995. No guarantee for correctness!

DISCiPLE's Logic									  

The MGT Disciple's address decoding logic consists of two (one time programmable) PAL chips type 20L8, which are connected are shown here. IC8 has 15 inputs and 7 outputs while IC9 has 14 inputs and 8 outputs. Note that IC8 has three output pins that are not connected, and that IC8 and IC9 are mutually connected by three wires. 
These chips sometimes are called DUM and DEE. 
		          		 		          
p18-IC9	 1	|	|24	+5V	  A9	 1	|	|24	+5V
p17-IC9	 2	|   IC8	|23	A11	  A5	 2	|   IC9	|23	/M1 
    A10	 3	|	|22>	p14-IC9 (help)	  A6	 3	|	|22>	PdataCLK (printer)
     A8	 4	| PAL20L8	|21>	n.c.	  A7	 4	| PAL20L8	|21>	WAIT (=/WAIT-Z80!)
     A4	 5	|	|20>	ROMCS(=/ROMCS-Z80!) /WR	 5	|	|20>	240EN (joy2)
 /RESET	 6	|  'DUM'	|19>	n.c.	 /RD	 6	|  'DEE'	|19>	244EN (joy1)
    /WR	 7	|	|18>	n.c.	/IORQ	 7	|	|18>	p1-IC8 (patch)
    /RD	 8	|	|17	inhib	  A3	 8	|	|17>	p2-IC8 (boot)
  /MREQ	 9	|	|16>	ROMCE	  A2	 9	|	|16>	WD1772
    A12	10	|	|15>	RAMCE	  A1	10	|	|15>	374CLK
    A13	11	|	|14	A14	  A0	11	|	|14	p22-IC8 /help
    Gnd	12	|        	|13	A15	 Gnd	12	|        	|13	NET (connector)

Output p22 of IC8 holds a signal (help) that is decoded from a set of Z80 signals. This signal is used for every function that is realized in IC9.
Output p17 of IC9 holds a signal (boot) that is fed to the 'BOOT' flipflop residing in IC8. This flipflop controls the position of the ROM and RAM chips in the 16K disciple system. The status of the BOOT flipflop is reflected by the hardware signals /ROMCE and /RAMCE. 
Output p18 of IC9 holds a signal (patch) that is fed to the 'PATCH' flipflop which also resides in IC8. This flipflop defines whether the Spectrum ROM is paged in or the Disciple's ROM/RAM system, by means of the hardware signal ROMCS. 
The outputs of IC8 that are not wired belong to the two flipflops and are electrically connected inside the chip. 

Bolean equations as disassembled from the fuse maps of IC 8 and IC9 (see app.A)	

The equations relate to output pins and follow the general form of /x = (n AND m) OR (o AND p AND q) OR ... (brackets only for clarity). The relative polarity of n, m, o, p and q can be positive or negative. The resulting x must always be negative (/x) for a type 20L8 PAL, as the outputs have a fixed negative polarity! 

The relative polarity of a signal is defined by the following table:
	  from	>      EQUATION
	PIN LIST	|     m          /m      		This follows the rule:
	   m	|    pos.        neg.	      	      //m = m               
	  /m	|    neg.        pos.

In consistancy with this rules the PAL output pins that are connected to the Z80-signals '/ROMCS' and '/WAIT' are named 'ROMCS' and 'WAIT'. As the inverted quality of these signals, like the other output signals, follows from the equations.
Names for output and inputs in each equation relate to the same chip. (IC8 or IC9) 
Notation in order of priority:  '/' = Inverted, '*' = AND, "+" = OR.

IC9 DEE   (Note that 'help' is the inverted '/help' signal decoded in IC8 DUM)
====================================================================================
/240EN = /A7 * /A6 * /A5 * help * A3 * A2 * A1 * A0 * RD * IORQ * /M1
As 'help' holds '//A4', the address is 00011111 = 31 
pin /IORQ must be low as the signal is not inverted, pin /M1 must be high 
= Read Joystick 2  			IN 31  	IC9-20

/374CLK = /A7 * /A6 * /A5 * help * A3 * A2 * A1 * A0 * WR * IORQ * /M1
As 'help' holds '//A4', the address is 00011111 = 31  
pin /IORQ must be low as the signal is not inverted, pin /M1 must be high 
= Enable inhibit latch 374		OUT 31   	IC9-15

/244EN = A7 * A6 * A5 * help * A3 * A2 * A1 * /A0 * RD * IORQ * /M1
As 'help' holds '//A4', the address is 11111110 = 254
pin /IORQ must be low as the signal is not inverted, pin /M1 must be high 
= Joystick 1		 		IN 254  	IC9-19

/PdataCLK = A7 * A6 * A5 * help * A3 * /A2 * A1 * A0 * WR * IORQ * /M1
As 'help' holds '//A4', the address is 11111011 = 251 
pin /IORQ must be low as the signal is not inverted, pin /M1 must be high 
= Latch printer data in LS374  	OUT 251   	IC9-22

/WAIT = /A7 * /A6 * A5 * help * A3 * /A2 * A1 * A0 * WR * IORQ * /M1 * NET
As 'help' holds '//A4', the address is 00111011 = 59 
pin /IORQ must be low as the signal is not inverted, pin /M1 must be high 
Also the 'NET' bit must be SET.
= Wait for network data		OUT 59   	IC9-21 

/WD1772 = /A5 * help * A3 * /A2 * A1 * A0 * IORQ * /M1
As 'help' holds '//A4', the address is xx011011 = 27,91,155,219 
pin /IORQ must be low as the signal is not inverted, pin /M1 must be high 
= Enable Floppy controller WD1772	IN/OUT 27,91,155,219   IC9-16

/boot = /A7 * A6 * A5 * help * A3 * /A2 * A1 * A0 * IORQ * /M1 *
As 'help' holds '//A4', the address is 01111011 = 123 
pin /IORQ must be low as the signal is not inverted, pin /M1 must be high 
= Generate the '/boot' signal	IN/OUT 123	IC9-17 
  Read and Write are taken into account at the receiving end: See IC8-NC18+NC19

/patch = /A9 * /A7 * /A6 * /A5 * /help * /A3 * /A2 * /A1 * A0 * RD */IORQ * M1 *
As '/help' holds /A4, /A8, /A10-/A15, the address is 0000000000000001 = 1 
pin /IORQ must be high as the signal is inverted, pin /M1 must be low = valid
       + /A9 * /A7 * /A6 * /A5 * /help * A3 * /A2 * /A1 * /A0 * RD */IORQ * M1 *
As '/help' holds /A4, /A8, /A10-/A15, the address is 0000000000001000 = 8 
pin /IORQ must be high as the signal is inverted, pin /M1 must be low = valid 
	+ /A9 * /A7 * A6 * A5 * /help * /A3 * A2 * A1 * /A0 * RD */IORQ * M1 *
As '/help' holds /A4, /A8, /A10-/A15, the address is 0000000001100110 = 102 
pin /IORQ must be high as the signal is inverted, pin /M1 must be low =valid
	+ A9 * A7 * /A6 * /A5 * /help * A3 * A2 * A1 * /A0 * RD */IORQ * M1 *
As '/help' holds /A4, /A8, /A10-/A15, the address is 0000001010001110 = 654 
pin /IORQ must be high as the signal is inverted, pin /M1 must be low = valid
	+ A7 * /A6 * A5 * help * A3 * /A2 * A1 * A0 *IORQ * /M1 *
As 'help' holds '//A4', the address is 10111011 = 187 
pin /IORQ must be low as the signal is not inverted, pin /M1 must be high 
= Generate the '/patch' signal			IC9-18
  This takes place when an 'opcode fetch' (see the polarity of M1)
  occurs at addresses 8,1,654,102  OR during IN/OUT 187 where Read and Write are
  taken into account at the receiving end: IC8-/ROMCS+NC21
  Read also the more elaborate explanation at IC8-/help

IC8 DUM      (Note that the 'patch' and 'boot' signals are decoded in IC9 DEE)
====================================================================================
/help =    /A4 * /MREQ * RD 
	+ /A4 * /MREQ * WR
	+ /A4 * MREQ * RD * /A15 * /A14 * /A13 * /A12 * /A11 * /A10 * /A8
= Generate the (negative) '/help' signal
  This is done at all (R+W) I.O. instructions (as //MREQ=hi) where A4 is low, 
  OR during a Read in the address range: 000000x0xxx0xxxx = 0 - 751. This signal 
  is used for all functions composed in IC9.		IC8-22
-----------------------------------------------------------------------------------
Note that for the paging addresses defined in the '/patch' equation (IC9) only the third term of '/help' is valid because pin /MEMRQ is expected to be low as the signal is not inverted, and the other two terms expect the pin /MREQ to be inverted = high. 
For all the I.O. addresses the inverted signal 'help' is taken into account.

Now when /help = A + B + C, then help = /A * /B * /C	 (DeMorgan's theorem).
Each term in turn now can be rewritten as (again DeMorgan): 
(first term as example)	                
  		  		help =	/A4 * RD * /MREQ =  A4 + /RD + MREQ
This leads to:
       help = (A4+MREQ+/RD)*(A4+MREQ+/WR)*(A4+MREQ+/RD+A15+A14+A13+A12+A11+A10+A8)
In fact this equation describes all the situations in which /help is false. 
It can bee seen that 'help' is valid as soon as A4 is high (as A4 occurs in all terms), and that the combination of /RD-/WR-MEMRQ-/MEMRQ signals block any other valid situation.
-----------------------------------------------------------------------------------

/NC21 =		 ROMCS
	+ /patch * RD * inhib
/ROMCS = 		 NC21
    	+ /inhib
    	+ RESET
    	+ /patch * WR
= Page-in/out Flipflop. 			IC8-20/21
  These outputs have there inverted signals mutually connected, so only one of these
  outputs can be low at the time. Such logic element is called a flipflop.
  For paging-in the Disciple, ROMCS has to be positive thus /NC21 valid = negative. 
Disciple will page-in (see /NC21) when 'inhib' is high AND a Read to one of the 'patch addresses takes place. With a Write to one of the 'patch' addresses (in fact only OUT 187) OR RESET going low (see pin name) OR inhib going low, the Disciple system pages out (see /ROMCS).

/NC19 =	NC18
	+ RESET
    	+ /boot * RD
/NC18 = 	NC19
    	+ /boot * WR
= ROM/RAM Flipflop. 				IC8-18/19
  These outputs have there inverted signals mutually connected, so only one of these
  outputs can be low at the time. Such logic element is called a flipflop.
NC19 will go low when pin /RESET goes low OR a Read takes place from the 'boot' address 123. Then NC18 will go high, and ROM is found the in 0-8K range.(see /ROMCE and /RAMCE)
A Write to the 'boot' address 123 will move ROM to 8-16 and RAM to 0-8.

/ROMCE = ROMCS * NC18 * RD * MREQ * /A13 * /A14 * /A15
    	 + ROMCS * NC19 * RD * MREQ * A13 * /A14 * /A15
When 'NC18' is high then ROM is selected in the address range 0-8K, (A13=lo)
When 'NC19' is high then ROM is selected in the address range 8-16K, (A13=hi)
both only during a Read.			IC8-16

/RAMCE = ROMCS * NC18 * RD * MREQ * A13 * /A14 * /A15
    	 + ROMCS * NC18 * WR * MREQ * A13 * /A14 * /A15
	 + ROMCS * NC19 * RD * MREQ * /A13 * /A14  * /A15
    	 + ROMCS * NC19 * WR * MREQ * /A13 * /A14  * /A15
When 'NC18' is high then RAM is selected in the address range 8-16K, (A13=hi)
When 'NC19' is high then RAM is selected in the address range 0-8K, (A13=lo)
both during Read and Write. 		IC8-15

Appendix A											
Fuse maps read from IC8 and IC9	

IC8						IC9
L0000 	1111111111111111111111111111111111111111	1111111111111111111111111111111111111111
L0040 	1111111111111011111111111011011111111111	0111010101111011111110110111101101010111
L0080 	1111111111111011111110111111011111111111	0000000000000000000000000000000000000000
L0120 	1111101010111011111111111011101110101010	0000000000000000000000000000000000000000
L0160 	0000000000000000000000000000000000000000	0000000000000000000000000000000000000000
L0200 	0000000000000000000000000000000000000000	0000000000000000000000000000000000000000
L0240 	0000000000000000000000000000000000000000	0000000000000000000000000000000000000000
L0280 	0000000000000000000000000000000000000000	0000000000000000000000000000000000000000
L0320 	1111111111111111111111111111111111111111	1111111111111111111111111111111111111111
L0360 	1111111111111101111111111111111111111111	0111100110111011111110110111101101010101
L0400 	1110111111111111111111111001111111111111	0000000000000000000000000000000000000000
L0440 	0000000000000000000000000000000000000000	0000000000000000000000000000000000000000
L0480 	0000000000000000000000000000000000000000	0000000000000000000000000000000000000000
L0520 	0000000000000000000000000000000000000000	0000000000000000000000000000000000000000
L0560 	0000000000000000000000000000000000000000	0000000000000000000000000000000000000000
L0600 	0000000000000000000000000000000000000000	0000000000000000000000000000000000000000
L0640 	1111111111111111111111111111111111111111	1111111111111111111111111111111111111111
L0680 	1111111111111111111111111110111111111111	1011100110111111101110110111011101010111
L0720 	1111111111011111111111111111111111111111	0000000000000000000000000000000000000000
L0760 	1111111111111111101111111111111111111111	0000000000000000000000000000000000000000
L0800 	1110111111111111111110111111111111111111	0000000000000000000000000000000000000000
L0840 	0000000000000000000000000000000000000000	0000000000000000000000000000000000000000
L0880 	0000000000000000000000000000000000000000	0000000000000000000000000000000000000000
L0920 	0000000000000000000000000000000000000000	0000000000000000000000000000000000000000
L0960 	1111111111111111111111111111111111111111	1111111111111111111111111111111111111111
L1000 	1111111111111111111111011111111111111111	0111010101111111101110110111011101011011
L1040 	1111111111111111101111111111111111111111	0000000000000000000000000000000000000000
L1080 	1011111111111111111111111011111111111111	0000000000000000000000000000000000000000
L1120 	0000000000000000000000000000000000000000	0000000000000000000000000000000000000000
L1160 	0000000000000000000000000000000000000000	0000000000000000000000000000000000000000
L1200	0000000000000000000000000000000000000000	0000000000000000000000000000000000000000
L1240 	0000000000000000000000000000000000000000	0000000000000000000000000000000000000000
L1280 	1111111111111111111111111111111111111111	1111111111111111111111111111111111111111
L1320 	1111111111111111110111111111111111111111	0111100101111111111110110111101101010111
L1360 	1011111111111111111110111111111111111111	1010101010111111101101110111101110101011
L1400 	0000000000000000000000000000000000000000	0110011010111111101101111011011101101011
L1440 	0000000000000000000000000000000000000000	1001101001111111101101110111011101101011
L1480 	0000000000000000000000000000000000000000	1010101010111111101101111011101110100111
L1520 	0000000000000000000000000000000000000000	0000000000000000000000000000000000000000
L1560 	0000000000000000000000000000000000000000	0000000000000000000000000000000000000000
L1600 	0000000000000000000000000000000000000000	1111111111111111111111111111111111111111
L1640 	0000000000000000000000000000000000000000	0111010110111111111110110111101101010111
L1680 	0000000000000000000000000000000000000000	0000000000000000000000000000000000000000
L1720 	0000000000000000000000000000000000000000	0000000000000000000000000000000000000000
L1760 	0000000000000000000000000000000000000000	0000000000000000000000000000000000000000
L1800 	0000000000000000000000000000000000000000	0000000000000000000000000000000000000000
L1840 	0000000000000000000000000000000000000000	0000000000000000000000000000000000000000
L1880 	0000000000000000000000000000000000000000	0000000000000000000000000000000000000000
L1920 	1111111111111111111111111111111111111111	1111111111111111111111111111111111111111
L1960 	1111111111111101111111011011101111101010	1011110111111111111110110111101101010111
L2000 	1111111111111101110111111011101111100110	0000000000000000000000000000000000000000
L2040 	0000000000000000000000000000000000000000	0000000000000000000000000000000000000000
L2080 	0000000000000000000000000000000000000000	0000000000000000000000000000000000000000
L2120 	0000000000000000000000000000000000000000	0000000000000000000000000000000000000000
L2160 	0000000000000000000000000000000000000000	0000000000000000000000000000000000000000
L2200 	0000000000000000000000000000000000000000	0000000000000000000000000000000000000000
L2240 	1111111111111111111111111111111111111111	1111111111111111111111111111111111111111
L2280 	1111111111111101110111111011101111101010	1011100110111011111110110111011101010111
L2320 	1111111111111101110110111111101111101010	0000000000000000000000000000000000000000
L2360 	1111111111111101111111011011101111100110	0000000000000000000000000000000000000000
L2400 	1111111111111101111110011111101111100110	0000000000000000000000000000000000000000
L2440 	0000000000000000000000000000000000000000	0000000000000000000000000000000000000000
L2480 	0000000000000000000000000000000000000000	0000000000000000000000000000000000000000
L2520 	0000000000000000000000000000000000000000	0000000000000000000000000000000000000000

Appendix B											
Port addresses used on Disciple, as given in the Disciple Manual and The Complete DISCiPLE disassembly								
	A7 A6 A5 A4 A3 A2 A1 A0
	0  0  0  1  1  0  1  1	= 27   WD1772 status/command
	0  1  0  1  1  0  1  1	= 91   WD1772 track
	1  0  0  1  1  0  1  1	= 155  WD1772 sector
	0  0  0  1  1  0  1  1	= 219  WD1772 data

	0  0  1  1  1  0  1  1	= 59   NET		--IN only
	0  1  1  1  1  0  1  1	= 123  Rom/Ram flip
	1  0  1  1  1  0  1  1	= 187  Page-in flip
	1  1  1  1  1  0  1  1	= 251  Printer		--OUT only

	0  0  0  1  1  1  1  1 = 31   In=Joystick1,    OUT=CONTROL latch
	1  1  1  1  1  1  1  0 = 254  IN=joystick2	--IN only
	0  0  0  0  0  0  0  1	= 1    page-in addr
	0  0  0  0  1  0  0  0	= 8    page-in addr
	0  1  1  0  0  1  1  0	= 102  page-in addr
01 1  0  0  0  1  1  1  1	= 654  page-in addr 

Appendix C											
Synchronicity of Z80 control signals
/MREQ * /RFSH	: during refresh
/MREQ * /RD * /M1	: during opcode fetch
/MREQ * (/RD + /WR)	: memory r/w
/IORQ * (/RD + /WR)	: port r/w
/IORQ * /M1	: acknowledge interrupt

***end